+ " .set mips3 \n" \
+ "1: ll %0, %1 \n" \
+ " .set mips0 \n" \
+ " subu %0, 1 # decrement \n" \
+ " .set mips3 \n" \
+ " sc %0, %1 \n" \
+ " .set mips0 \n" \
+ " beqz %0, 1b \n" \
+ : "=&r" (temp), "=m" (ref.count) \
+ : "m" (ref.count) \
+ : ); \
+ if (!ref) \
+ delete this; \
+ }
+ #elif defined(__ppc__) || defined(__powerpc__)
+ #define DECLARE_REF(x) \
+ public: void AddRef(); \
+ void Release(); \
+ private: oRefCount ref;
+ #define DEFINE_REF(c) \
+ void c::AddRef() \
+ { \
+ int temp; \
+ __asm__ __volatile__( \
+ "1: lwarx %0, 0, %3 \n" \
+ " add %0, %2, %0 \n" \
+ " dcbt 0, %3 # workaround for PPC405CR Errata\n" \
+ " stwcx. %0, 0, %3 \n" \
+ " bne- 1b \n" \
+ : "=&r" (temp), "=m" (ref.count) \
+ : "r" (1), "r" (&ref.count), "m" (ref.count) \
+ : "cc"); \
+ } \
+ void c::Release() \
+ { \
+ int temp; \
+ __asm__ __volatile__( \
+ "1: lwarx %0, 0, %3 \n" \
+ " subf %0, %2, %0 \n" \
+ " dcbt 0, %3 # workaround for PPC405CR Errata\n" \
+ " stwcx. %0, 0, %3 \n" \
+ " bne- 1b \n" \
+ : "=&r" (temp), "=m" (ref.count) \
+ : "r" (1), "r" (&ref.count), "m" (ref.count) \
+ : "cc"); \
+ if (!ref) \
+ delete this; \
+ }
+ #elif defined(__i386__) || defined(__x86_64__)
+ #define DECLARE_REF(x) \
+ public: void AddRef(); \
+ void Release(); \
+ private: oRefCount ref;
+ #define DEFINE_REF(c) \
+ void c::AddRef() \
+ { \
+ __asm__ __volatile__( \
+ " lock ; incl %0 \n" \
+ : "=m" (ref.count) \
+ : "m" (ref.count)); \
+ } \
+ void c::Release() \
+ { \
+ __asm__ __volatile__( \
+ " lock ; decl %0 \n" \
+ : "=m" (ref.count) \
+ : "m" (ref.count)); \